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Features
* 6.6 SPEC int 95, 5.5 SPECfp95 at 266 MHz (Estimated) * Superscalar 603e Core * Integer Unit (IU), Floating-Point Unit (FPU) (User Enabled or Disabled), Load/Store Unit * * * * * * * * * *
(LSU), System Register Unit (SRU), and a Branch Processing Unit (BPU) 16-Kbyte Instruction Cache 16-Kbyte Data Cache Lockable L1 Caches - Entire Cache or on a Per-way Basis up to 3 of 4 Ways Dynamic Power Management High-bandwidth Bus (32/64 bits Data Bus) to DRAM Supports 1-Mbyte to 1-Gbyte DRAM Memory 32-bit PCI Interface Operating up to 66 MHz PCI 2.1-compliant, 5.0V Tolerance Fint Max = 200 MHz FBus Max = 66 MHz
Integrated Processor Family PC8240
Description
The PC8240 combines a PowerPC TM 603e core microprocessor with a PCI bridge. The PC8240's PCI support will allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces. The PC8240 also integrates a highperformance memory controller which supports various types of DRAM and ROM. The PC8240 is the first of a family of products that provides system level support for industry standard interfaces with a PowerPC microprocessor core. The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, I2O controller, and a two-wire interface controller. The 603e core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. The 603e core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the PC8240's memory space are passed to the processor bus for snooping purposes when snoop mode is enabled. The PC8240's features serve a variety of embedded applications. In this way, the 603e core and peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or an agent controller.
Screening/Quality/Packaging
This product is manufactured in full compliance with: * Upscreening based upon Atmel standards * Industrial temperature range
(Tc = -40C, Tc = +110C) (Tc = -40C, Tc = +125C): ZD3 suffix
* * * Core power supply:
TP suffix
2.5 5 % V (L-Spec for 200 MHz)
I/O power supply: 3.0V to 3.6V 352 Tape Ball Grid Array (TBGA)
TBGA352 Tape Ball Grid Array
Rev. 2149A-HIREL-05/02
1
General Description
Block Diagram
Figure 1. Block Diagram
PC8240 Additional features: * JTAG/COP interface * Power management 603e Processor Core Block Processor PLL (64-bit) Two-instruction fetch
The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC 603e core, as shown in Figure 1.
Branch Processing Instruction Unit Unit (BPU) (64-bit) Two-instruction dispatch
System Register Unit (SRU)
Integer Unit (IU)
Load/Store Unit (LSU)
Floating Point Unit (FPU) 64-bit
Data MMU 16-Kbyte Data Cache
Instruction MMU 16-Kbyte Instruction Cache
Peripheral Logic Bus Peripheral Logic Block Message Controller (I2O) Address (32-bit) Central Control Unit Configuration Registers I2C I2C Controller EPIC Interrupt Controller /Timers PCI Bus Interface Unit Address Translator PCI Arbiter DLL Peripheral Logic PLL Fanout Buffers SDRAM Clocks PCI Clock In PCI Bus Clocks Data (64-bit) Data Path ECC Controller Data Bus (32- or 64-bit) with 8-bit Parity or ECC Memory/ROM/PortX Address and Control
Memory Controller
DMA Controller
5 IRQs/ 16 Serial Interrupts
32-bit Five Request/ PCI Interface Grant Pairs
Oscillator Input
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PC8240
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PC8240
Pinout Listing
Table 1 provides the pinout listing for the PC8240, 352 TBGA package.
Table 1. PC8240 Pinout Listing
Signal Name PCI Interface Signals C/BE[0 - 3] DEVSEL FRAME IRDY LOCK AD[0 - 31] A25 F23 K23 P25 H26 J24 K25 J26 C22 D22 B22 B23 D19 B24 A24 B26 A26 C26 D25 D26 E23 E25 E26 F24 L26 L25 M25 M26 N23 N25 N26 R26 R25 T26 T25 U23 U24 U26 U25 V25 G25 V26 W23 W24 W25 W26 AB26 AA25 AA26 Y25 Y26 G26 F26 H25 K26 AC26 P26 I/O I/O I/O I/O Input I/O OVdd OVdd OVdd OVdd OVdd OVdd DRV_PCI DRV_PCI DRV_PCI DRV_PCI - DRV_PCI
(6)(15) (8)(15) (8)(15) (8)(15) (8) (6)(15)
Package Pin Number
Pin Type
Power Supply
Output Driver Type
Notes
PAR GNT[0 - 3] GNT4/DA5 REQ[0 - 3] REQ4/DA4 PERR SERR STOP TRDY INTA IDSEL
I/O Output Output Input Input I/O I/O I/O I/O Output Input
OVdd OVdd OVdd OVdd OVdd OVdd OVdd OVdd OVdd OVdd OVdd
DRV_PCI DRV_PCI DRV_PCI - - DRV_PCI DRV_PCI DRV_PCI DRV_PCI DRV_PCI -
(15) (6)(15) (7)(15) (6)(12) (12) (8)(15)(18) (8)(15)(16) (8)(15) (8)(15) (15)(16)
-
Memory Interface Signals MDL[0 - 31] AD17 AE17 AE15 AF15 AC14 AE13 AF13 AF12 AF11 AF10 AF9 AD8 AF8 AF7 AF6 AE5 B1 A1 A3 A4 A5 A6 A7 D7 A8 B8 A10 D10 A12 B11 B12 A14 AC17 AF16 AE16 AE14 AF14 AC13 AE12 AE11 AE10 AE9 AE8 AC7 AE7 AE6 AF5 AC5 E4 A2 B3 D4 B4 B5 D6 C6 B7 C9 A9 B10 A11 A13 B13 A15 AB1 AB2 K3 K2 AC1 AC2 K1 J1 Y4 AA3 AA4 AC4 M2 L2 M1 L1 H1 N4 N2 I/O GVdd DRV_MEM_DATA
(5)(6)(13)
MDH[0 - 31]
I/O
GVdd
DRV_MEM_DATA
(6)(13)
CAS/DQM[0 - 7] RAS/CS[0 - 7] FOE RCS0 RCS1
Output Output I/O I/O Output
GVdd GVdd GVdd GVdd GVdd
DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR
(6) (6) (3)(4) (3)(4)
-
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Table 1. PC8240 Pinout Listing (Continued)
Signal Name SDMA[11 - 0] SDMA12/SDBA1 SDBA0 PAR[0 - 7] SDRAS SDCAS CKE WE AS EPIC Control Signals IRQ_0/S_INT IRQ_1/S_CLK IRQ_2/S_RST IRQ_3/S_FRAME IRQ_4/ L_INT C19 B21 AC22 AE24 A23 Input I/O I/O I/O I/O OVdd OVdd OVdd OVdd OVdd - DRV_PCI DRV_PCI DRV_PCI DRV_PCI - - - - - Package Pin Number N1 R1 R2 T1 T2 U4 U2 U1 V1 V3 W1 W2 P1 P2 AF3 AE3 G4 E2 AE4 AF4 D2 C2 AD1 AD2 H2 AA1 Y1 Pin Type Output Output Output I/O Output Output Output Output Output Power Supply GVdd GVdd GVdd GVdd GVdd GVdd GVdd GVdd GVdd Output Driver Type DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR Notes
(6)(14)
(14)
-
(6)(13)(14) (3) (3) (3)(4)
-
(3)(4)
Two-wire Interface Control Signals SDA SCL Clock Out Signals PCI_CLK[0 - 3] PCI_CLK4/DA3 PCI_SYNC_OUT PCI_SYNC_IN SDRAM_CLK[0 - 3] SDRAM_SYNC_OUT SDRAM_SYNC_IN CKO/DA1 OSC_IN Miscellaneous Signals HRST_CTRL HRST_CPU MCP NMI SMI SRESET A20 A19 A17 D16 A18 B16 Input Input Output Input Input Input OVdd OVdd OVdd OVdd OVdd OVdd - - DRV_STD - - - - -
(3)(4)(17)
AE20 AF21
I/O I/O
OVdd OVdd
DRV_STD DRV_STD
(10)(16) (10)(16)
AC25 AB25 AE26 AF25 AF26 AD25 AB23 D1 G1 G2 E1 C1 H3 B15 AD21
Output Output Output Input Output Output Input Output Input
GVdd GVdd GVdd GVdd GVdd GVdd GVdd OVdd OVdd
DRV_PCI_CLK DRV_PCI_CLK DRV_PCI_CLK - DRV_MEM_ADDR DRV_MEM_ADDR - DRV_STD -
(6)
- - -
(6)
- - - -
-
(10) (10)
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PC8240
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PC8240
Table 1. PC8240 Pinout Listing (Continued)
Signal Name TBEN QACK/DA0 CHKSTOP_IN MAA[0 - 2] MIV PMAA[0 - 2] Package Pin Number B14 F2 D14 AF2 AF1 AE1 A16 AD18 AF18 AE19 Pin Type Input Output Input Output Output Output Power Supply OVdd OVdd OVdd - OVdd OVdd Output Driver Type - DRV_STD - DRV_MEM_DATA DRV_STD DRV_STD Notes
(10) (3)(4) (10) (3)(4)(6)
-
(3)(4)(6)(15)
Test/Configuration Signals PLL_CFG[0 - 4]/ DA[10 - 6] TEST[0 - 1] TEST2 TEST3 TEST4 TCK TDI TDO TMS TRST A22 B19 A21 B18 B17 AD22 B20 Y2 AF20 AC18 AF22 AF23 AC21 AE22 AE23 Input Input Input Input I/O Input Input Output Input Input OVdd OVdd - OVdd OVdd OVdd OVdd OVdd OVdd OVdd - - - - DRV_STD - - DRV_PCI - -
(4)(6)
(1)(6)(9) (11) (10) (10) (9)(12) (9)(12)
-
(9)(12) (9)(12)
Power and Ground Signals GND AA2 AA23 AC12 AC15 AC24 AC3 AC6 AC9 AD11 AD14 AD16 AD19 AD23 AD4 AE18 AE2 AE21 AE25 B2 B25 B6 B9 C11 C13 C16 C23 C4 C8 D12 D15 D18 D21 D24 D3 F25 F4 H24 J25 J4 L24 L3 M23 M4 N24 P3 R23 R4 T24 T3 V2 V23 W3 AC20 AC23 D20 D23 G23 P23 Y23 Ground - - -
52 terminals
LVdd
Reference voltage 3.3V, 5.0V Power for Memory Drivers 2.5V, 3.3V PCI/Stnd 3.3V Power for Core 2.5V Power for DLL 2.5V
LVdd
-
-
GVdd
AB3 AB4 AC10 AC11 AC8 AD10 AD13 AD15 AD3 AD5 AD7 C10 C12 C3 C5 C7 D13 D5 D9 E3 G3 H4 K4 L4 N3 P4 R3 U3 V4 Y3 AB24 AD20 AD24 C14 C20 C24 E24 G24 J23 K24 M24 P24 T23 Y24 AA24 AC16 AC19 AD12 AD6 AD9 C15 C18 C21 D11 D8 F3 H23 J3 L23 M3 R24 T4 V24 W4 D17
GVdd
-
-
OVdd Vdd
OVdd Vdd
- -
- -
LAVdd
LAVdd
-
-
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Table 1. PC8240 Pinout Listing (Continued)
Signal Name AVdd Package Pin Number C17 Pin Type Power for PLL (CPU Core Logic) 2.5V Power for PLL (Peripheral Logic) 2.5V Power Supply AVdd Output Driver Type - Notes -
AVdd2
AF24
AVdd2
-
-
Manufacturing Pins DA2 DA[11 - 13] C25 AD26 AF17 AF19 I/O I/O OVdd OVdd DRV_PCI DRV_PCI
(2) (2)(6)
(2)(6) DA[14 - 15] F1 J2 I/O GVdd DRV_MEM_ADDR Notes: 1. Place pull-up resistors of 120 or less on the TEST[0 - 1] pins. 2. Treat these pins as No Connects unless using debug address functionality. 3. This pin has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a "1" is read into configuration bits during reset. 4. This pin is a reset configuration pin. 5. DL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a "1" is read into configuration bits during reset. 6. Multi-pin signals such as AD[0 - 31] or DL[0 - 31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin C22, AD1 is on pin D22,... AD31 is on pin V25. 7. GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8240 is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a "1" is read into configuration bits during reset. 8. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this PCI control pin to LVdd. 9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 6, "DC Electrical Specifications," on page 16. 10. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to OVdd. 11. Recommend a weak pull-up resistor (2 k - 10 k) be placed on this pin to GVdd. 12. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 13. Output Valid specifications for this pin are memory interface mode dependent (Registered or Flow-through), see Table 11, "Output AC Timing Specifications," on page 22. 14. Non-DRAM Access Output Valid specification applies to this pin during non-DRAM accesses, see specification 12b3 in Table 11, "Output AC Timing Specifications," on page 22. 15. This pin is affected by programmable PCI_HOLD_DEL parameter, see "PCI Signal Output Hold Timing" on page 23. 16. This pin is an open drain signal. 17. This pin can be programmed to be driven (default) or can be programmed to be open drain; see PMCR2 register description in the Motorola PC8240 User's Manual for details. 18. This pin is a Sustained Tri-State pin as defined by the PCI Local Bus Specification.
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PC8240
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PC8240
Detailed Specification Scope Applicable Documents Requirements
General Design and Construction
Terminal Connections The terminal connections are shown in Table 1, "PC8240 Pinout Listing," on page 3. The microcircuits are in accordance with the applicable documents and as specified herein. This drawing describes the specific requirements for the PC8240 processor, in compliance with Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535: General specifications for microcircuits.
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
Symbol Vdd GVdd OVdd AVdd/AVdd2/LAVdd VIN LVdd TSTG Notes: Characteristic(1) Supply Voltage - CPU Core and Peripheral Logic Supply Voltage - Memory Bus Drivers Supply Voltage - PCI and Standard I/O Buffers Supply Voltage - PLLs and DLL Supply Voltage - PCI Reference Input Voltage(2) Storage Temperature Range Value -0.3 to 2.75 -0.3 to 3.6 -0.3 to 3.6 -0.3 to 2.75 -0.3 to 3.6 -0.3 to 5.4 -55 to 150 Unit V V V V V V C
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. PCI inputs with LVdd = 5V 5% V DC may be correspondingly stressed at voltages exceeding LVdd + 0.5V DC.
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Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Symbol Vdd OVdd GVdd Characteristic(1) Supply Voltage I/O Buffer supply for PCI and Standard Supply Voltages for Memory Bus Drivers Recommended Value 2.5 5 % 3.3 0.3 3.3 5 % 2.5 5 % AVdd AVdd2 LAVdd LVdd PLL Supply Voltage - CPU Core Logic PLL Supply Voltage - Peripheral Logic DLL Supply Voltage PCI Reference 2.5 5 % 2.5 5 % 2.5 5 % 55% 3.3 0.3 VIN Input Voltage PCI Inputs All Other Inputs TC Notes: Operating Temperature 0 to 3.6 or 5.75 0 to 3.6 -40 to 125 Unit V V V V V V V V V V V C Notes
(5) (5) (7) (7) (5) (6) (6) (8)(9) (8)(9) (2)(3) (4)
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PCI pins are designed to withstand LVdd + 0.5V DC when LVdd is connected to a 5.0V DC power supply. 3. PCI pins are designed to withstand LVdd + 0.5V DC when LVdd is connected to a 3.3V DC power supply. 4. Caution: Input voltage (VIN) must not be greater than the supply voltage (Vdd/AVdd/AVdd2/LAVdd) by more than 2.5V at all times including during power-on reset. 5. Caution: OVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8V at any time including during power-on reset. 6. Caution: Vdd/AVdd/AVdd2/LAVdd must not exceed OVdd by more than 0.6V at any time including during power-on reset. 7. Caution: GVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8V at any time including during power-on reset. 8. Caution: LVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 5.4V at any time including during power-on reset. 9. Caution: LVdd must not exceed OVdd by more than 3.6V at any time including during power-on reset.
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PC8240
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PC8240
Figure 2. Supply Voltage Sequencing and Separation Cautions
DC Power Supply Voltage
5V 10 9
LVdd at 5V
(1)
3.3V 2.5V
7
10 9 6.8
OVdd/GVdd/(LVdd@3.3V ----) Vdd/AVdd/AVdd2/LAVdd
Vdd Stable
100 ms PLL Relock Time (3)
0 Voltage Regulator Delay (2) HRST_CPU & HRST_CTRL asserted 255 external memory Clock cycles (3)
Time
Power Supply Ramp Up (2)
Reset Configuration Pins
9 external memory clock cycles setup time (4)
HRST_CPU & HRST_CTRL
Maximum rise time must be less than one external memory clock cycle (5)
VM = 1.4V
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, "Recommended Operating Conditions," on page 8. 2. Refer to "Power Supply Voltage Sequencing" on page 35 for additional information. 3. Refer to Table 9 on page 18 for additional information on PLL Relock and reset signal assertion timing requirements. 4. Refer to Table 10 on page 20 for additional information on reset configuration pin setup timing requirements. 5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the non-reset state.
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Figure 3 shows the undershoot and overshoot voltage of the memory interface of the PC8240. Figure 3. Overshoot/Undershoot Voltage
4V GVdd + 5% GVdd
VIH
VIL
Gnd Gnd 0.3V Gnd 1.0V
Not to exceed 10% of tSDRAM_CLK
Thermal Information
Thermal Characteristics Table 4. Package Thermal Characteristics
Symbol JC JB Characteristic Die Junction-to-Case Thermal Resistance Die Junction-to-Board Thermal Resistance Min 1.8 4.8 Unit C/W C/W
Thermal Management Information
This section provides thermal management information for the tape ball grid array (TBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design, the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see Figure 4. Figure 4. Package Exploded Cross-Sectional View with Several Heat Sink Options
Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Die TBGA Package
Printed-Circuit Board
Option
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PC8240
Figure 5 depicts the die junction-to-ambient thermal resistance for four typical cases: 1. A heat sink is not attached to the TBGA package and there exists high boardlevel thermal loading of adjacent components. 2. A heat sink is not attached to the TBGA package and there exists low boardlevel thermal loading of adjacent components. 3. A heat sink (e.g. ChipCoolers #HTS255-P) is attached to the TBGA package and there exists high board-level thermal loading of adjacent components. 4. A heat sink (e.g. ChipCoolers #HTS255-P) is attached to the TBGA package and there exists low board-level thermal loading of adjacent components. Figure 5. Die Junction-to-Ambient Resistance
18 Die Junction- to- Ambient Thermal Resistance (* ring* C/ W)
No heat sink and high thermal board-level loading of adjacent components No heat sink and low thermal board-level loading of adjacent components Attached heat sink and high thermal board-level loading of adjacent components
16
14
Attached heat sink and low thermal board-level loading of adjacent components
12
10
8
6
4
2 0 0.5 1 1.5 2 2.5 Airflow Velocity (m/s)
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The board designer can choose between several types of heat sinks to place on the PC8240. There are several commercially-available heat sinks for the PC8240 provided by the following vendors:
Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 Thermalloy 2021 W. Valley View Lane Dallas, TX 75234-8993 Wakefield Engineering 100 Cummings Center, Suite 157H Beverly, MA 01915 Aavid Engineering 250 Apache Trail Terrell, TX 75160 800-227-0254 (USA/Canada) 401-739-7600 Internet: www.chipcoolers.com 818-842-7277 Internet: www.ctscorp.com 972-243-4321 Internet: www.thermalloy.com 781-406-3000 Internet: www.wakefield.com 972-551-7330 Internet: www.aavid.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Internal Package Conduction Resistance For the TBGA, cavity down, packaging technology, shown in Figure 4 on page 10, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case thermal resistance, The die junction-to-ball thermal resistance.
Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 6. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
External Re sistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads
Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance)
For this cavity-down, wire-bond TBGA package, heat generated on the active side of the chip is conducted through the silicon, the die attach and package spreader, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection.
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PC8240
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PC8240
Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 7 shows the thermal performance of three thinsheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 6). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors, thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. Figure 7. Thermal Performance of Select Thermal Interface Material
2
Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease
Specific Thermal Resistance (Kin2/W)
1.5
1
0.5
0 0 10 20 30 40 50 60 70 80 Contact Pressure (PSI)
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2149A-HIREL-05/02
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors:
Dow-Corning Corporation Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4014 Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067-3910 800-248-2481 Internet: www.dow.com
781-935-4850 Internet: www.chomerics.com 888-246-9050 Internet: www.thermagon.com 860-571-5100 Internet: www.loctite.com
Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: TJ = TA + TR + (JC + INT + SA) x PD Where: TJ is the die-junction temperature. TA is the inlet cabinet ambient temperature. TR is the air temperature rise within the computer cabinet. JC is the junction-to-case thermal resistance. INT is the adhesive or interface material thermal resistance. SA is the heat sink base-to-ambient thermal resistance. PD is the power dissipated by the device. During operation the die-junction temperatures (TJ) should be maintained less than the value specified in Table. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (TA) may range from 30 to 40C. The air temperature rise within a cabinet (TR) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (INT) is typically about 1C/W. Assuming a TA of 30C, a TR of 5C, a TBGA package JC = 1.8, and a power consumption (PD) of 5.0 watts, the following expression for TJ is obtained: Die-junction temperature: TJ = 30C + 5C + (1.8C/W + 1.0C/W + SA) x 5.0W For preliminary heat sink sizing, the heat sink base-to-ambient thermal resistance is needed from the heat sink manufacturer. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow.
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PC8240
The final die-junction operating temperature, is not only a function of the componentlevel thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature-airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request.
Power Consideration
Table 5 provides preliminary power consumption data for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 5. Preliminary Power Consumption
PCI Bus Clock/Memory Bus Clock CPU Clock Frequency (MHz) Mode Typical Max - FP Max - INT Doze Nap Sleep 33/66/166 2.5 3.0 2.7 1.8 700 500 33/66/200 2.8 3.4 3.0 2.0 700 500 33/100/200 3.0 3.6 3.3 2.2 900 500 66/100/200 3.0 3.6 3.4 2.2 900 800 Unit W W W W mW mW Notes
(1)(5) (1)(2) (1)(3) (1)(4)(6) (1)(4)(6) (1)(4)(6)
I/O Power Supplies Mode Typ - OVdd Typ - GVdd Notes: Minimum 200 300 Maximum 600 900 Unit mW mW Notes
(7)(8) (7)(9)
1. The values include Vdd, AVdd, AVdd2, and LVdd but do not include I/O Supply Power, see "Power Supply Sizing" on page 36 for information on OVdd and GVdd supply power. 2. Maximum - FP power is measured at Vdd = 2.625V with dynamic power management enabled while running an entirely cacheresident, looping, floating point multiplication instruction. 3. Maximum - INT power is measured at Vdd = 2.625V with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. Power saving mode maximums are measured at Vdd = 2.625V while the device is in doze, nap, or sleep mode. 5. Typical power is measured at Vdd = AVdd = 2.5V, OVdd = 3.3V where a nominal FP value, a nominal INT value, and a value where there is a continuous flush of cache lines with alternating ones and zeroes on 64-bit boundaries to local memory are averaged. 6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled. 7. The typical minimum I/O power values were results of the PC8240 performing cache resident integer operations at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. 8. The typical maximum OVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:200 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory.
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9. The typical maximum GVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:200 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes on 64-bit boundaries to local memory. Note: To calculate the power consumption at low temperature (-55C), use a 1.25 factor.
Marking
The document where markings are defined is identified in the related reference documents. Each microcircuit is legible and permanently marked with the following information as minimum: * * * * Atmel Logo, Manufacturer's part number,Date-code of inspection lot, ESD identifier if available, Country of manufacturing.
Electrical Characteristics
Static Characteristics
Table 6 provides the DC electrical characteristics for the PC8240. At recommended operating conditions (see Table 3 on page 8) Table 6. DC Electrical Specifications
Value Characteristics
(1) (4)
Conditions PCI only PCI only
Symbol VIH VIL VIH VIH VIL CVIH CVIL
Min 0.5*OVdd - 2.0 1.8 GND 0.5*OVdd GND - - - 2.4 - 1.85 - -
Max LVdd 0.3*OVdd 3.3 2.5 0.8 - 0.3*OVdd 70 TBD 10 - 0.4 - 0.6 7.0
Unit V V V V V V V A A A V V V V pF
Input High Voltage Input Low Voltage Input High Voltage Input High Voltage Input Low Voltage PCI_SYNC_IN Input High Voltage PCI_SYNC_IN Input Low Voltage Input Leakage Current using DRV_PCI driver
(5)
All other pins (GVdd = 3.3V) All other pins (GVdd = 2.5V) All inputs except OSC_IN
for pins
0.5V VIN 2.7V at LVdd = 4.75 0.5V VIN 5.5V at LVdd = 5.5 LVdd = 3.6V GVdd = 3.465 IOH = N/A (GVdd = 3.3V)(3) IOL = N/A (GVdd = 3.3V)(3) IOH = N/A (GVdd = 2.5V) IOL = N/A (GVdd = 2.5V) VIN = 0V, f = 1 MHz
(3) (3)
IL IL IL VOH VOL VOH VOL CIN
Input Leakage Current(5) for pins using DRV_PCI driver Input Leakage Current(5) all others Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Capacitance(2) Notes:
1. See Table 1 on page 3 for pins with internal pull-up resistors. 2. Capacitance is periodically sampled rather than 100% tested.
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3. See Table 7 on page 17 for the typical drive capability of a specific signal pin based upon the type of output driver associated with that pin as listed in. 4. These specifications are for the default driver strengths indicated in Table. 5. Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is measured for nominal OVdd/LVdd and Vdd or both Ovdd/LVdd and Vdd must vary in the same direction.
Table 7 provides information on the characteristics of the output drivers referenced in. The values are from the PC8240 IBIS model (v1.0) and are not tested, for additional detailed information see the complete IBIS model listing at http://www.mot.com/SPS/PowerPC/ teksupport/tools/IBIS/kahlua_1.ibs.txt Table 7. Drive Capability of PC8240 Output Pins
Driver Type DRV_STD Programmable Output Impedance (Ohms) 20 40 (default) DRV_PCI 25 Supply Voltage (V) OVdd = 3.3 OVdd = 3.3 LVdd = 3.3 LVdd = 5.0 50 (default) LVdd = 3.3 LVdd = 5.0 DRV_MEM_ADDR DRV_PCI_CLK 8 (default) GVdd = 2.5 GVdd = 3.3 13.3 GVdd = 2.5 GVdd = 3.3 20 GVdd = 2.5 GVdd = 3.3 40 GVdd = 2.5 GVdd = 3.3 DRV_MEM_DATA 20 (default) GVdd = 2.5 GVdd = 3.3 40 GVdd = 2.5 GVdd = 3.3 Notes: IOH TBD TBD 11.0 5.6 5.6 5.6 TBD 89.0 TBD 55.9 TBD 36.7 TBD TBD TBD 36.7 TBD 18.7 IOL TBD TBD 20.6 10.3 10.3 10.3 TBD 73.3 TBD 46.4 TBD 30.0 TBD TBD TBD 30.0 TBD 15.0 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Notes
(2)(5) (2)(5) (1)(4) (1)(4) (1)(4) (1)(4) (3)(6) (2)(5) (3)(6) (2)(5) (3)(6) (2)(5) (3)(6) (2)(5) (3)(6) (2)(5) (3)(6) (2)(5)
1. For DRV_PCI, IOH read from the listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the 0.3V and 0.4V table entries' current values which correspond to the PCI VOH = 2.97 = 0.9*LVdd (LVdd = 3.3V) where Table Entry Voltage = LVdd - PCI VOH. 2. For all others with OVdd or GVdd = 3.3V, IOH read from the listing in the pull-up mode, I(Min) column, at the 0.9V table entry which corresponds to the VOH = 2.4V where Table Entry Voltage = O/GVdd - PCI VOH. 3. For GVdd = 2.5V, IOH read from the listing in the pull-up mode, I(Min) column, at the TBDV table entry which corresponds to the VOH = TBD V where Table Entry Voltage = GVdd - VOH. 4. For DRV_PCI, IOL read from the listing in the pull-down mode, I(Max) column, at 0.33V = PCI VOL = 0.1*LVdd (LVdd = 3.3V) by interpolating between the 0.3V and 0.4V table entries. 5. For all others with OVdd or GVdd = 3.3V, IOL read from the listing in the pull-down mode, I(Max) column, at the 0.4V table entry. 6. For GVdd = 2.5V, IOL read from the listing in the pull-down mode, I(Max) column, at the TBDV table entry.
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Dynamic Electrical Characteristics
This section provides the AC electrical characteristics for the PC8240. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 9, "Clock AC Timing Specifications," on page 18 and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0-4] signals. Parts are sold by maximum processor core frequency; see "Ordering Information" on page 41. Table 8 provides the operating frequency information for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 8. Operating frequency
200 MHz Characteristic(1) Processor Frequency (CPU) Memory Bus Frequency PCI Input Frequency Note: Min 100 25 - 100 25 - 66 Max 200 Unit MHz MHz MHz
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0 - 4] settings must be chosen such that the resulting peripheral logic/memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0 - 4] signal description in "PLL Configuration" on page 34 for valid PLL_CFG[0 - 4] settings and PCI_SYNC_IN frequencies.
Clock AC Specifications
Table 9 provides the clock AC timing specifications as defined in Section. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 9. Clock AC Timing Specifications
Num 1a 1b 2, 3 4 5a 5b 7 8a 8b 10 15 16 17 Characteristics and Conditions(1) Frequency of Operation (PCI_SYNC_IN) PCI_SYNC_IN Cycle Time PCI_SYNC_IN Rise and Fall Times PCI_SYNC_IN Duty Cycle Measured at 1.4V PCI_SYNC_IN Pulse Width High Measured at 1.4V PCI_SYNC_IN Pulse Width Low Measured at 1.4V PCI_SYNC_IN Short Term Jitter (Cycle to Cycle) PCI_CLK[0 - 4] Skew (Pin to Pin) SDRAM_CLK[0 - 3] Skew (Pin to Pin) Internal PLL Relock Time DLL Lock Range with DLL_EXTEND = 0 disabled (Default) DLL Lock Range with DLL_EXTEND = 1 enabled Frequency of Operation (OSC_IN) Min 25 40 - 40 6 6 - 0 TBD - Max 66 15 2.0 60 9 9 < 500 500 TBD 100 Unit MHz ns ns % ns ns ps ps ps s ns ns MHz
(8) (3)(4)(6) (7) (7) (3) (3) (2)
Notes
0 (NTclk - tloop - tfix0) 7 0 (NTclk - Tclk/2 - tloop - tfix0) 7 25 66
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Table 9. Clock AC Timing Specifications (Continued)
Num 18 19 20 21 22 23 Notes: Characteristics and Conditions(1) OSC_IN Cycle Time OSC_IN Rise and Fall Times OSC_IN Duty Cycle Measured at 1.4V OSC_IN Frequency Stability OSC_IN VIH (Loaded) OSC_IN VIL (Loaded) 1. 2. 3. 4. 5. Min 40 - 40 - TBD - TBD Max 15 5 60 100 Unit ns ns % ppm V V
(5)
Notes
These specifications are for the default driver strengths indicated in Table 7 on page 17. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4V. Specification value at maximum frequency of operation. Relock time is guaranteed by design and characterization. Relock time is not tested. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not tested. 6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable Vdd and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence. 7. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1, 2, 3, ...). Tclk is the period of one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. tfix0 is a fixed delay inherent in the design when the DLL is at tap point 0 and the DLL is contributing no delay; tfix0 equals approximately 3 ns. See Figure 9 on page 20 for DLL locking ranges. 8. Pin to pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, i.e. the amount of variance between the internal sys-logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin to pin skew between SDRAM_CLKs can be measured, the relationship between the internal sys-logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
Figure 8. PCI_SYNC-IN Input Clock Timing Diagram
1 5a 5b 2 3
CVIL PCI_SYNC_IN VM VM VM CVIH VM = Midpoint Voltage (1.4V)
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Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation
DLL will lock DLL not guaranteed to lock Tclk SDRAM_ SYNC_ OUT Period and Frequency 25 MHz 40 ns N=1 DLL_EXTEND = 1
33 MHz 30 ns
50 MHz 20 ns
N=1 DLL_EXTEND = 0
100 MHz 10 ns 0 ns 5 ns 10 ns Tloop Propagation Delay Time in Nanoseconds
N=2 DLL_EXTEND = 1 N=2 DLL_EXTEND = 0 15 ns
Input AC Timing Specifications
Table 10 provides the input AC timing specifications. See Figure 10 on page 21 and Figure 11 on page 21. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 10. Input AC Timing Specifications
Num 10a 10b1 10b2 10c 10d 10e 11a 11b Notes: Characteristics PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) Memory Control and Data Input Signals in Flow Through Mode Valid to SDRAM_SYNC_IN (Input Setup) Memory Control and Data Input Signals in Registered Mode Valid to SDRAM_SYNC_IN (Input Setup) Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup) Min 2.0 4.0 TBD TBD TBD 9*tCLK 1.0 TBD Max - - - - - - - - Unit ns ns ns ns ns ns ns ns Notes
(2)(3) (1)(3)
(1)(3)
(1)(3) (1)(3) (1)(3)(5) (1)(2)(3) (1)(3)(5)
Two-wire Interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
Mode select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup) PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold) HRST_CPU/HRST_CTRL to Mode select Inputs Invalid (Input Hold)
1. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21.
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2. All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the signal in question for 3.3V PCI signaling levels. See Figure 11. 3. Input timings are measured at the pin. 4. tCLK is the time of one SDRAM_SYNC_IN clock cycle. 5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 12.
Figure 10. Input - Output Timing Diagram Referenced to SDRAM_SYNC_IN
PCI_SYNC_IN
SDRAM_SYNC_IN shown in 2:1 mode
VM
VM
VM
10b-d 11a 2.0V 12b-d 2.0V 13b 14b
MEMORY INPUTS/OUTPUTS
0.8V 0.8V
Input Timing
Output Timing
VM = Midpoint Voltage (1.4V)
Figure 11. Input - Output Timing Diagram Referenced to PCI_SYNC_IN
PCI_SYNC_IN
OVdd/2 OVdd/2 OVdd/2
10a 12a 11a 13a 14a 0.615*OVdd 0.4*OVdd 0.285*OVdd
PCI INPUTS/OUTPUTS
Input Timing
Output Timing
Figure 12. Input Timing Diagram for Mode Select Signals
HRST_CPU/HRST_CTRL
VM
10e
11b 2.0V
MODE PINS
0.8V
VM = Midpoint Voltage (1.4V)
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Output AC Timing Specification
Table 11 provides the processor bus AC timing specifications for the PC8240. See Figure 10 on page 21 and Figure 11 on page 21. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 11. Output AC Timing Specifications
Num 12a Characteristics(3)(6) PCI_SYNC_IN to Output Valid, 66 MHz PCI, with MCP pulled-down to logic 0 state. See Figure 14. PCI_SYNC_IN to Output Valid, 33 MHz PCI, with MCP in the default logic 1 state. See Figure 14. 12b1 SDRAM_SYNC_IN to Output Valid (For Memory Control and Data Signals accessing DRAM in Flow Through Mode) SDRAM_SYNC_IN to Output Valid (For Memory Control and Data Signals accessing DRAM in Registered Mode) SDRAM_SYNC_IN to Output Valid (For Memory Control and Data Signals accessing non-DRAM) SDRAM_SYNC_IN to Output Valid (For All Others) SDRAM_SYNC_IN to Output Valid (For Two-wire Interface) Output Hold, 66 MHz PCI, with MCP and CKE pulled-down to logic 0 states. See Table 12. Output Hold, 33 MHz PCI, with MCP in the default logic 1 state and CKE pulled-down to logic 0 state. See Table 12. 13b 14a 14b Notes: Output Hold (For All Others) PCI_SYNC_IN to Output High Impedance (For PCI) SDRAM_SYNC_IN to Output High Impedance (For All Others) Min - - - Max 6.0 8.0 7.0 Unit ns ns ns Notes
(2)(4)
(2)(4)
(1)
12b2
-
TBD
ns
(1)
12b3 12c 12d 13a
- - - 0.5 2.0 0 - -
TBD 7.0 TBD - - - TBD TBD
ns ns ns ns ns ns ns ns
(1)
(1) (1) (2)(4)(5)
(2)(4)(5)
(1) (2)(4) (1)
1. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21. 2. All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.285*OVdd or 0.615*OVdd of the signal in question for 3.3V PCI signaling levels. See Figure 11 on page 21. 3. All output timings assume a purely resistive 50 load (See Figure 13 on page 23). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0 - 3], PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD[0 - 31], REQ[4 - 0], GNT[4 - 0], IDSEL, INTA. 5. PCI hold times can be varied, see "PCI Signal Output Hold Timing" on page 23 for information on programmable PCI output hold times. The values shown for item 13a are for PCI compliance. 6. These specifications are for the default driver strengths indicated in Table 7 on page 17.
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Figure 13. AC Test Load for the PC8240
Output measurements are made at the device pin OUTPUT PIN
Z0 = 50 RL = 50
OVdd/2
PCI Signal Output Hold Timing
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the PC8240 has a programmable output hold delay for PCI signals. The initial value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals. Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register. Table 12 describes the bit values for the PCI_HOLD_DEL values in PMCR2.
Table 12. Power Management Configuration Register 2-0x72
Bit 6-4 Name PCI_HOLD_DEL Reset value xx0 Description PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5 are determined by the reset configuration pins MCP and CKE, respectively. As these two pins have internal pull-up resistors, the default value after reset is 0b110. While the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or decrementing the value in these bit fields of this register via software or hardware configuration. The increment is in approximately 400 picosecond steps. Lowering the value in the three bit field decreases the amount of output hold available. 000 66 MHz PCI. Pull-down MCP configuration pin with a 2K or less value resistor. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 11 are met for a 66 MHz PCI system. See Figure 14 on page 24. 001 010 011 100 33 MHz PCI. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 11 are met for a 33 MHz PCI system. See Figure 14 on page 24. 101 110 (Default if reset configuration pins left unconnected) 111
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Figure 14. PCI_HOLD_DEL Affect on Output Valid and Hold Time
PCI_SYNC_IN
12a, 8 ns for 33 MHz PCI PCI_HOLD_DEL = 100
0Vdd 2
0Vdd 2
13a, 2 ns for 33 MHz PCI PCI_HOLD_DEL = 100
PCI INPUTS/OUTPUTS 33 MHz PCI
12a, 6 ns for 66 MHz PCI PCI_HOLD_DEL = 000
13a, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 000
PCI INPUTS/OUTPUTS 66 MHz PCI
As PCI_HOLD_DEL values decrease
PCI INPUTS and OUTPUTS
As PCI_HOLD_DEL values increase
Diagram Not to Scale
OUTPUT VALID
OUTPUT HOLD
Two-wire Interface AC Timing Specifications
Table 13 provides the two-wire interface input AC timing specifications for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 13. Two-wire Interface Input AC Timing Specifications
Num 1 2 Characteristics Start condition hold time Clock low period (The time before the PC8240 will drive SCL low as a transmitting slave after detecting SCL low as driven by an external master.) Min 4.0 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) - 0 - Max - - Unit CLKs CLKs Notes
(1)(2) (1)(2)(4)(5)
3 4 5
SCL/SDA rise time (from 0.5V to 2.4V) Data hold time SCL/SDA fall time (from 2.4V to 0.5V)
1 - 1
mS ns mS
(2)
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Table 13. Two-wire Interface Input AC Timing Specifications (Continued)
Num 6 Characteristics Clock high period (Time needed to either receive a data bit or generate a START or STOP.) Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 5.0 Max - Unit CLKs Notes
(1)(2)(5)
7 8 9 Notes:
3.0 4.0 4.0
- - -
ns CLKs CLKs
(3) (1)(2)
(1)(2)
1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 16 on page 27. 3. Timing is relative to the Sampling Clock (not SCL). 4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. 5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine the maximum two-wire interface input frequency. See Figure 16 on page 27.
Table 14 provides the two-wire interface Frequency Divider Register (I2CFDR) information for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5% and LVdd = 3.3V 5% Table 14. PC8240 Maximum Two-wire Interface Input Frequency
Max Two-wire Interface Input Frequency(1) FDR Hex(2) 20, 21 22, 23, 24, 25 0, 1 2, 3, 26, 27, 28, 29 4, 5 6, 7, 2A, 2B, 2C, 2D 8, 9 A, B, 2E, 2F, 30, 31 C, D E, F, 32, 33, 34, 35 10, 11 12, 13, 36, 37, 38, 39 Divider (Dec)(2) 160, 192 224, 256, 320, 384 288, 320 384, 448, 480, 512, 640, 768 576, 640 768, 896, 960, 1024, 1280, 1536 1152, 1280 1536, 1792, 1920, 2048, 2560, 3072 2304, 2560 3072, 3584, 3840, 4096, 5120, 6144 4608, 5120 6144, 7168, 7680, 8192, 10240, 12288 SDRAM_CLK at 25 MHz 862 555 409 324 229 177 121 92 62 47 32 24 SDRAM_CLK at 33 MHz 1.13 MHz 733 540 428 302 234 160 122 83 62 42 31 SDRAM_CLK at 50 MHz 1.72 MHz 1.11 MHz 819 649 458 354 243 185 125 95 64 48 SDRAM_CLK at 100 MHz 3.44 MHz 2.22 MHz 1.63 MHz 1.29 MHz 917 709 487 371 251 190 128 96
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Table 14. PC8240 Maximum Two-wire Interface Input Frequency (Continued)
Max Two-wire Interface Input Frequency(1) FDR Hex(2) 14, 15 16, 17, 3A, 3B, 3C, 3D 18, 19 1A, 1B, 3E, 3F 1C, 1D 1E, 1F Notes: Divider (Dec)(2) 9216, 10240 12288, 14336, 15360, 16384, 20480, 24576 18432, 20480 24576, 28672, 30720, 32768 36864, 40960 49152, 61440 SDRAM_CLK at 25 MHz 16 12 8 6 4 3 SDRAM_CLK at 33 MHz 21 16 10 8 5 4 SDRAM_CLK at 50 MHz 32 24 16 12 8 6 SDRAM_CLK at 100 MHz 64 48 32 24 16 12
1. Values are in kHz unless otherwise specified. 2. FDR Hex and Divider (Dec) values are listed in corresponding order. 3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique output frequency as shown in Table 15 on page 26.
Table 15 provides the two-wire interface output AC timing specifications for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5% and LVdd = 3.3V 5% Table 15. Two-wire Interface Output AC Timing Specifications
Num 1 2 3 4 Characteristics Start condition hold time Clock low period SCL/SDA rise time (from 0.5V to 2.4V) Data hold time Min (FDR[5] == 0) x (DFDR/16)/2N + (FDR[5] == 1) x (DFDR/16)/2M DFDR/2 - 8.0 + (16 x 2FDR[4:2]) x (5 4({FDR[5],FDR[1]} == b'10) 3({FDR[5],FDR[1]} == b'11) 2({FDR[5],FDR[1]} == b'00) 1({FDR[5],FDR[1]} == b'01)) Max - - - - Unit CLKs CLKs mS CLKs Notes
(1)(2)(5)
(1)(2)(5) (3) (1)(2)(5)
5 6 7 8 9 Notes:
SCL/SDA fall time (from 2.4V to 0.5V) Clock high time Data setup time (PC8240 as a master only) Start condition setup time (for repeated start condition only) Stop condition setup time DFDR/2 (DFDR/2) - (Output data hold time) DFDR + (Output start condition hold time) 4.0
<5 - - - -
ns CLKs CLKs CLKs CLKs
(4) (1)(2)(5) (1)(5) (1)(2)(5)
(1)(2)
1. Units for these specifications are in SDRAM_CLK units. 2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 16 on page 27. 3. Since SCL and SDA are open-drain type outputs, which the PC8240 can only drive low, the time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
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4. Specified at a nominal 50 pF load. 5. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to the two-wire interface Interface chapter's Serial Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.
Figure 15. Two-wire Interface Timing Diagram I
2 SCL VM VM 6 1 SDA 4
Figure 16. Two-wire Interface Timing Diagram II
5 SCL VM VH VL 8 SDA 9 3
Figure 17. Two-wire Interface Timing Diagram III
DFFSR FILTER CLK (1) 7 SDA INPUT DATA VALID
Note 1: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.
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2149A-HIREL-05/02
Figure 18. Two-wire Interface Timing Diagram IV (Qualified signal)
SCL/SDArealtime VM
Delay (1) SCL/SDAqualified VM
Note 1: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.
EPIC Serial Interrupt Mode AC Timing Specifications
Table 16 provides the EPIC serial interrupt mode AC timing specifications for the PC8240. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5% and LVdd = 3.3V 5%
Table 16. EPIC Serial Interrupt Mode AC Timing Specifications
Num 1 2 3 4 5 6 7 Notes: Characteristics S_CLK Frequency S_CLK Duty Cycle S_CLK Output Valid Time Output Hold Time S_FRAME, S_RST Output Valid Time S_INT Input Setup Time to S_CLK S_INT Inputs Invalid (Hold Time) to S_CLK Min 1/14 SDRAM_SYNC_IN 40 - 0 - 1 sys_logic_clk period + TBD - Max 1/2 SDRAM_SYNC_IN 60 TBD = x - 1 sys_logic_clk period + x - 0 Unit MHz % nS nS nS nS nS
(2)
Notes
(1)
(2) (2)
1. See the PC8240 User's Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency programming. 2. S_RST, S_FRAME, and S_INT shown in Figure 19 and Figure 20 depict timing relationships to sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the Motorola's PC8240 User's Manual for a complete description of the functional relationships between these signals. 3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See Motorola's PC8240 User's Manual for a complete clocking description.
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PC8240
2149A-HIREL-05/02
PC8240
Figure 19. EPIC Serial Interrupt Mode Output Timing Diagram
sys_logic_clk3 VM 3 VM VM VM VM
4
S_CLK
5 S_FRAME VM S_RST
4 VM
Figure 20. EPIC Serial Interrupt Mode Input Timing Diagram
S_CLK VM 7 6 S_INT
IEEE 1149.1 (JTAG) AC Timing Specifications
Table 17 provides the JTAG AC timing specifications for the PC8240 while in the JTAG operating mode. At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V 5%
and LVdd = 3.3V 5%
Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)
Num Characteristics(4) TCK Frequency of Operation 1 2 3 4 5 6 7 8 9 TCK Cycle Time TCK Clock Pulse Width Measured at 1.5V TCK Rise and Fall Times TRST_ Setup Time to TCK Falling Edge TRST_ Assert Time Input Data Setup Time Input Data Hold Time TCK to Output Data Valid TCK to Output High Impedance Min 0 40 20 0 10 10 5 15 0 0 Max 25 - - 3 - - - - 30 30 Unit MHz ns ns ns ns ns ns ns ns ns
(2) (2) (3) (3) (1)
Notes
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Table 17. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)
Num 10 11 12 13 Notes: Characteristics(4) TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK to TDO Data Valid TCK to TDO High Impedance 1. 2. 3. 4. Min 5 15 0 0 Max - - 15 15 Unit ns ns ns ns Notes
TRST is an asynchronous signal. The setup time is for test purposes only. Non-test (other than TDI and TMS) signal input timing with respect to TCK. Non-test (other than TDO) signal output timing with respect to TCK. Timings are independent of the system clock (PCI_SYNC_IN).
Figure 21. JTAG Clock Input Timing Diagram
1 2 TCK 3 3 VM = Midpoint Voltage VM VM 2 VM
Figure 22. JTAG TRST Timing Diagram
TCK 4 TRST_ 5
Figure 23. JTAG Boundary Scan Timing Diagram
TCK
6 DATA INPUTS 8 DATA OUTPUTS 9 DATA OUTPUTS
7
INPUT VALID DATA
OUTPUT VALID DATA
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PC8240
2149A-HIREL-05/02
PC8240
Figure 24. Test Access Port Timing Diagram
TCK
10 TDI, TMS 12 TDO 13 TDO
11
INPUT VALID DATA
OUTPUT VALID DATA
Preparation for Delivery
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
Certificate of Compliance Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range.
Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: * * * * * * Devices should be handled on benches with conductive and grounded surfaces. Ground test equipment, tools and operator. Do not handle devices by the leads. Store devices in conductive foam or carriers. Avoid use of plastic, rubber or silk in MOS areas. Maintain relative humidity above 50% if practical.
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Package Description
Package Parameters
The PC8240 uses a 35 mm x 35 mm, cavity down, 352 pin Tape Ball Grid Array (TBGA) package. The package parameters are as provided in the following list. Table 18. Package Parameters
Parameter Package Outline Interconnects Pitch Solder Balls Solder Balls Diameter Maximum Module Height Co-planarity Specification Maximum Force 35 mm x 35 mm 352 1.27 mm 63/37 Sn/Pb 0.75 mm 1.65 mm 0.15 mm 6.0 lbs. total, uniformly distributed over package (8 grams/ball)
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PC8240
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PC8240
Mechanical Dimensions
Figure 25 shows the top surface, side profile, and pinout of the PC8240, 352 TBGA package.
Figure 25. PC8240 Package Dimensions and Pinout Assignments
-FCORNER
B
-E0.150
-TT
A
Top View
A B C D G H K L
Min Max 34.8 35.2 34.8 35.2 1.45 1.65 0.60 0.90 1.27 BASIC 0.85 0.95 31.75 BASIC 0.70 0.50
26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A C E G J L N R U W B D F H K M P T V
K
Y AA AB AC AD AE AF
C H L Bottom View 352X j D K G
Notes:
1. 2.
Drawing not to scale. All measurements are in millimeters (mm).
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PLL Configuration
The PC8240's internal PLLs are configured by the PLL_CFG[0-4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the Peripheral Logic/Memory Bus PLL (VCO) frequency of operation for the PCI-to-Memory frequency multiplying and the 603e CPU PLL (VCO) frequency of operation for Memoryto-CPU frequency multiplying. The PLL configuration for the PC8240 is shown in Table 19.
Table 19. PC8240 Microprocessor PLL Configuration
200 MHz Part(9) PLL_ CFG [0 - 4](1)(3) 00000 00001 00010 00011 00100 00101 00111 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11101 11110 11111 CPU HID1 [0 - 4](2) 00110 TBD TBD TBD 00101 TBD TBD 11000 TBD 00110 11000 00100 00100 11110 11010 11000 11010 11000 00110 TBD TBD 25 - 40 25 - 33 25 - 33 33(8) - 66 25 - 28 25 25 - 26 50 3 - 44 33(8) - 53 33(7) - 56(6) 25 - 28(6) 50 - 56(6)
PCI Clock Input (PCI_ SYNC_IN) Range(1) (MHz) Periph Logic/ Mem Bus Clock Range (MHz) CPU Clock Range (MHz)
Ratios (4)(5)
PCI to Mem (Mem VCO) Multiplier Mem to CPU (CPU VCO) Multiplier
Ref 0 1 2 3 4 5 7 8 A C E 10 12 14 16 18 1A 1C 1D 1E 1F Notes:
25 - 26
75 - 80 NOT USABLE 50 - 56 Bypass 50 - 56 Bypass Bypass 33 - 56 NOT USABLE 50 - 80 50 - 66 75 - 100 50 - 100 50 - 56 50 62 - 65 50 50 - 66 50 - 80
188 - 200
3(6) 3(6)
2.5(5) 3(6) 2(8) 2(8) 2(8) 2.5(5) 3(6) 3(6) 4.5(9) 2.5(5) 3(6) 2(4) 2(4) 3.5(7) 4(8) 3(6) 4(8) 3(6) 2.5(5) Off Off
100 - 112
1(4) Bypass
100 - 113
2(8) Bypass Bypass
100 - 168
1(4) 2(4)
125 - 200 150 - 200 150 - 200 100 - 200 175 - 200 200 186 - 200 200 150 - 200 125 - 200
2(4) 2(4) 3(6) 1.5(3) 2(4) 2(4) 2.5(5) 1(2) 1.5(3) 1.5(3) Off Off
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0 - 4] settings must be chosen such that the resulting peripheral logic/ memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum or minimum operating frequencies shown in Table. Bold font numerical pairs indicate input range limit and limiting parameter. 2. The processor HID1 values only represent the multiplier of the processor's PLL (Memory to Processor Multiplier), thus multiple PC8240 PLL_CFG[0 - 4] values may have the same processor HID1 value. This implies that system software cannot read the HID1 register and associate it with a unique PLL_CFG[0 - 4] value. 3. PLL_CFG[0 - 4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011) are reserved. 4. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for factory use only. The AC timing specifications given in this document do not apply in PLL Bypass mode.
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PC8240
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PC8240
5. 6. 7. 8. 9. In Clock Off mode, no clocking occurs inside the PC8240 regardless of the PCI_SYNC_IN input. Limited due to maximum memory VCO = 225 MHz. Limited due to minimum CPU VCO = 200 MHz. Limited due to minimum memory VCO = 100 MHz. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
System Design Information
PLL Power Supply Filtering
This section provides electrical and thermal design recommendations for successful application of the PC8240. The AVdd, AVdd2, and LAVdd power signals are provided on the PC8240 to provide power to the peripheral logic/memory bus PLL, the 603e processor PLL, and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal clocks, the power supplied to the AVdd, AVdd2, and LAVdd input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. A separate circuit similar to the one shown in Figure 26 using surface mount capacitors with minimum effective series inductance (ESL) is recommended for each of the AVdd, AVdd2, and LAVdd power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. The circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important but proportionately less critical for the LAVdd pin. Figure 26. PLL Power Supply Filter Circuit
10 k Vdd 2.2 F 2.2 F Low ESL surface mount capacitors GND AVdd, AVdd2, or LAVdd
Power Supply Voltage Sequencing
The notes in Table 3 on page 8 contain cautions illustrated in Figure 2 on page 9 about the sequencing of the external bus voltages and internal voltages of the PC8240. These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward biased and excessive current can flow through these diodes. Figure 2 shows a typical ramping voltage sequence where the DC power sources (voltage regulators and/or power supplies) are connected as shown in Figure 27. The voltage regulator delay shown in Figure 2 can be zero if the various DC voltage levels are all applied to the target board at the same time. The ramping voltage sequence shows a scenario in which the Vdd/AVdd/AVdd2/LAVdd power plane is not loaded as much as the OVdd/GVdd power plane and thus Vdd/AVdd/AVdd2/LAVdd ramps at a faster rate than OVdd/GVdd. If the system power supply design does not control the voltage sequencing, the circuit of Figure 27 can be added to meet these requirements. The MUR420 diodes of Figure 27 control the maximum potential difference between the 3.3 bus and internal voltages on power-up and the 1N5820 Schottky diodes regulate the maximum potential difference on power-down.
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2149A-HIREL-05/02
Figure 27. Example Voltage Sequencing Circuits
+ 5V Source + 3.3V Source + 2.5V Source + 5V + 3.3V IN5820 + 2.5V IN5820 + 3.3V MUR420 MUR420 + 2.5V
Power Supply Sizing
The power consumption numbers provided in Table do not reflect power from the OVDD and GVdd power supplies which are nonnegligible for the PC8240. In typical application measurements, the OV DD power ranged from 200 to 600 mW and the GVdd power ranged from 300 to 900 mW. The ranges' low end power numbers were results of the PC8240 performing cache resident integer operations at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz. The OVdd high end range's value resulted from the PC8240 performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory. The GVdd high end range's value resulted from the PC8240 operating at the fastest frequency combination of 66:100:200 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes on 64-bit boundaries to local memory. Due to the PC8240's dynamic power management feature, large address and data buses, and high operating frequencies, the PC8240 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC8240 system, and the PC8240 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd, OVdd, GVdd, and LVdd pin of the PC8240. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, GVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd, OVdd, GVdd, and LVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors - 100 - 330 F (AVX TPS tantalum or Sanyo OSCON).
Decoupling Recommendations
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, GVdd, LVdd and GND pins of the PC8240. The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of the PC8240.
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PC8240
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PC8240
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the SDRAM_SYNC_IN input of the PC8240. The trace length may be used to skew or adjust the timing window as needed. See Motorola application note AN1794/D for more information on this topic. Pull-up/Pull-down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The data bus signals are: DH[0 - 31], DL[0 - 31], and PAR[0 - 7]. If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0 - 31], and PAR[4 - 7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. The TEST[0 - 1] pins require pull-up resistors of 120 or less connected to OVdd. It is recommended that TEST2 have weak pull-up resistor (2 k - 10 k) connected to GVdd. It is recommended that the following signals be pulled up to OVdd with weak pull-up resistors (2 k - 10 k): SDA, SCL, SMI, SRESET, TBEN, CHKSTOP_IN, TEST3, and TEST4. It is recommended that the following PCI control signals be pulled up to LVdd with weak pull-up resistors (2 k - 10 k): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. The following pins have internal pull-up resistors enabled at all times: REQ[0 - 3], REQ4/DA4, TCK, TDI, TMS, and TRST. See Table 1, "PC8240 Pinout Listing," on page 3 for more information. The following pins have internal pull-up resistors enabled only while device is in the reset state: GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0 - 2], PMAA[0 - 2]. See Table 1, "PC8240 Pinout Listing," on page 3 for more information. The following pins are reset configuration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0 - 2], PMAA[0 - 2], and PLL_CFG[0 - 4]/DA[10 - 6]. These pins are sampled during reset to configure the device. Reset configuration pins should be tied to GND via 1 k pull-down resistors to ensure a logic zero level is read into the configuration bits during reset if the default logic one level is not desired. Any other unused active low input pins should be tied to a logic one level via weak pullup resistors (2 k - 10 k) to the appropriate power supply listed in Table 3 on page 8. Unused active high input pins should be tied to GND via weak pull-down resistors (2 k - 10 k).
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2149A-HIREL-05/02
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC8240 are available on the internet at www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is optional in the IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply tying TRST to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset signals on the PC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to guarantee normal operation. The common on-chip processor (COP) function of PowerPC processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 28 allows the COP to independently assert HRST_CPU/HRST_CTRL or TRST while ensuring that the target can drive HRST_CPU/HRST_CTRL as well. The shown COP header, adds many benefits including breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface. Availability of these features can be as inexpensive as an unpopulated footprint for a header to be added when needed.
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PC8240
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PC8240
Figure 28. COP Connector Diagram
PC8240 From Target SRESET Board Sources HRESET (if only) SRESET HRST_CPU HRST_CTRL 13 11 HRESET SRESET
10 k 10 k 10 k
1 3 5 7 9 11 13 15 2 4 6 8 10 12
OVdd OVdd OVdd OVdd TRST
10 k
4 6 52 153
Key 144
TRST
1.5 k
GND OVdd
VDD_SENSE
2 k 10 k 10 k 10 k
OVdd OVdd OVdd CKSTP_IN TMS TDO TDI TCK QACK1
Key No pin
16
8 COP Connector Physical Pin Out COP Header 9 1 3 7 2 10 12 16
CKSTP_IN TMS TDO TDI TCK NC NC NC
Notes:
1. QACK is an output on the PC8240 and is not required at the COP header for emulation. 2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the PC8240. Connect pin 5 of the COP header to OVdd with a 10K pull-up resistor. 3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the PC8240. Connect pin 15 of the COP header to OVdd with a 10K pull-up resistor. 4. Pin 14 is not physically present on the COP header. 5. Component not populated.
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2149A-HIREL-05/02
The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a "Berg" header). The connector typically has pin 14 removed as a connector key, as shown in Figure 28. There is no standardized way to number the COP header shown in Figure 28 on page 39; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin one (as with an IC). Regardless of the numbering, the signal placement recommended in is common to all known emulators.
Definitions
Datasheet Status Description
Table 20. Datasheet Status
Datasheet Status Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase
Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values
Valid during the design phase Valid before characterization phase
Valid before the industrialization phase Valid for production purposes
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification.
Life Support Applications
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.
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PC8240
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PC8240
Differences with Commercial Part
Table 21. Differences with commercial part
Commercial Part Temperature range Power consumption Spec 13a (output hold) 1 ns Tc = 0 to 105C Industrial Part Tc = -40 to 110C or Tc = -40 to 125 use a 1.25 factor to calculate at low temperature (-55C) 0.5 ns
Ordering Information
PC8240 V TP U 200 E (ZD3)
Type (PCX8240 if prototype) Temperature Range: Tc V: -40C, +110C Package TP: TBGA Screening Level(1) U: Upscreening
Extended temperature TC = -40C to 125C Revision Level Max Internal Processor Speed(1) 200: 200 MHz
Note: 1. For availability of the different versions, contact your ATMEL sale office.
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2149A-HIREL-05/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. The PowerPC names and the PowerPC logotype are trademarks of International Business Machines Corporation, used under license therform. Motorola is the registered trademark of Motorola, Inc. Other terms and product names may be the trademarks of others.
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